1. Technical Field
Various embodiments of the present invention relate to a semiconductor device technology, and more specifically, to a three-dimensional (3D) semiconductor device and methods of manufacturing and operating the same.
2. Related Art
Due to limitations in integration, a two-dimensional semiconductor device has been substituted by a 3D semiconductor device. The two-dimensional semiconductor device has a structure in which memory cells are arranged in a horizontal direction along a semiconductor substrate. On the other hand, in the 3D semiconductor device, memory cells are stacked in a direction perpendicular to a semiconductor substrate.
Each of the memory cells of the 3D semiconductor device may include either a floating structure or a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure. The SONOS structure is more general, and when the SONOS structure is applied, a drain selection transistor is connected between a bit line and a memory cell group, and a source selection transistor is connected between a source line and the memory cell group.
In the 3D semiconductor device, since the drain and source selection transistors have the same structure as the memory cells, the drain and source selection transistors have threshold voltages increased by a certain level to perform a function as a switching element after forming stack layers for the drain and source selection transistors.
Since the drain selection transistor performs a function of transferring a voltage transmitted from a bit line to a cell string, or electrically cutting the cell string off the bit line, a leakage current should not be generated from the drain selection transistor. To this end, two or more drain selection transistors coupled in series may be formed.
In such case, since gates of the two or more drain selection transistors are connected to the same drain selection line, the same voltage is applied to the gates of the two or more drain selection transistors. In this structure, due to a junction overlap between the drain selection transistors formed on an upper portion and a lower portion, an effective channel length in the drain selection transistor formed on the upper portion may be reduced. As a result, a leakage current in the drain selection transistor formed on the upper portion may be larger than that in the drain selection transistor formed on the lower portion. When the leakage current becomes large, reliability of a semiconductor device may be degraded since program disturbance characteristics in a program operation may be deteriorated.